Quite honestly it's the kind of workload I'd have expected to move into network ASICs as IP blocks, but that's a hosting customer decision and I'm not sure which hyperscalers expose programmable fabrics today to customers.
Nearly every protection-related instruction -- far CALL, far JMP, far RET, INT, IRET, MOV to segment register, task switch -- needs to load a segment descriptor from the GDT or LDT. The 386 microcode centralizes this into a shared subroutine called LD_DESCRIPTOR, which reads the 8-byte descriptor from memory and feeds the high DWORD (containing Type, DPL, S, and P bits) to the Test PLA for validation.
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